skip to Main Content
Edge AI Evangelist’s Thoughts Vol.5: Latest Trends In Non-Volatile FPGAs

Hello everyone, I’m Haruyuki Tago, Edge Evangelist at HACARUS Tokyo R&D Center.

In this series of articles, I will share some insights from my decades long experience in the semiconductor industry and comment on different AI industry related topics from my unique perspective.

Today let’s talk about the latest trends in the field of non-volatile FPGAs.


NV-FPGA Initiative – Public Symposium

On January 8th, 2021, a public symposium was held by Non-Volatile Field-Programmable Gate Array (NV-FPGA) Initiative, one of the themes of the AIST Consortium [1], a thematic study group run by the National Institute of Advanced Industrial Science and Technology (AIST). I am not a member of the study group, but will briefly report the highlights of the symposium from the perspective of an attendee.

Presentation program

  1. “CMOS annealing machine that accelerates combinatorial optimization processing and its FPGA implementation” by Mr. Masanao Yamaoka from Hitachi, Ltd.
  2. “About the realization of RISC-V based on Microchip’s non-volatile FPGA” by Mr. Nobuhisa Ikeda from Macnica
  3. “Latest Trends in Atomic Switch FPGA Technology” by Mr. Toshiji Sakamoto from NanoBridge Semiconductor
  4. “FPPARB Component Technology for Intelligent Robot Systems” by Mr. Takeshi Okawa, Tokai University
  5. Panel discussion “The future of non-volatile switch FPGA”

Moderator: NV-FPGA Initiative Secretariat Takeo Matsumoto

Lectures 1 and 4 were about new computer systems using FPGAs, and Lectures 2 and 3 were about new non-volatile FPGA devices.

In this article, we will first review the basic structure of FPGAs and the importance of switches, and then I’d like to talk about the new non-volatile FPGA devices based on the contents of lectures 2 and 3.


Fundamental structure of FPGA and importance of switch

Figure 1 shows the basic structure of the FPGA (Field Programmable Gate Array) chip. It consists of a large number of logic blocks arranged in a grid and a switch matrix. The internal circuit of the logic block is shown on the left of Figure 2.

The switch matrix can connect vertical wiring (blue) and horizontal wiring (light green) that are pre-built in the semiconductor chip at the desired position using a switch  configured using a CMOS transfer gate (Figure 2, right). This allows the user to freely connect between logic blocks.


Figure 1 Basic structure of FPGA


Each logic block consists of a LUT (Look-Up Table), D Flip-flop, MUX, etc. that can be programmed into any combinatory logic function (Figure 2, left). The LUT configuration sets the logical function of the LUT. MUX select chooses whether to use Flip-flops or not.

By setting the LUT configuration and MUX select with a switch, the logic block becomes the desired logic circuit. The logic block is called CLB (Configurable Logic Block) by Xilinx, LE (Logic Element) by Intel, and LE (Logic Element) by Microsemi.


Figure 2 Left: Logic block internal circuit, Right: Switch using CMOS transfer gate


As can be seen from Figures 1 and 2, FPGAs use so many switches that the reliability and area they occupy are important factors in determining the performance of an FPGA device. There is the (A) SRAM method, (B) Flash Cell method, and (C) Antifuse method for switch on / off information storage (Figure 3) [2].


Figure 3 Left: SRAM wiring program, Center: FLASH wiring program, Right: Antifuse wiring program. Created by the author based on [2].

Next, I would like to explain about non-volatile FPGA devices based on the contents of Lecture 2 and Lecture 3 at the above-mentioned symposium.


“Realization of RISC-V based on Microchip’s non-volatile FPGA”

Let’s take a look at the content of a lecture entitled “Realization of RISC-V based on Microchip’s non-volatile FPGA” by Mr. Nobuhisa Ikeda from Macnica Finesse Company, a semiconductor technology trading company.

Figure 4 Application example assuming RT Polar Fire from Microsemi [7]

FPGA product lineup

Figure 5 shows the Microchip product lineup.

Figure 5 Microchip FPGA and SoC FPGA Product Family [3]

Figure 5 Microchip FPGA and SoC FPGA Product Family [3]

In addition to the above table, PolarFire SoC was announced in 2020 [4]. PolarFire’s built-in CPU core was softcore RISC-V (32bit, 100-125MHz operation, using 10kLE), but in PolarFire SoC, hardcore RISC-V’s SiFive 64-bit multi-CPU cluster (4 + 1core, maximum 667MHz operation) is installed.

Linux runs in a configurable secure IoT system [5]. Comparing the power consumption required to obtain the CoreMark value of 6500, it is less than half that of the CPU cores used by competitors. The development tool is Libero SoC FPGA Design Flow, and the evaluation kit has been released.

FPGA wiring method

PolarFire SoC uses the Flash method (center of Figure 3) to store switch information. In the SRAM method (Xilinx, Intel), the SRAM information is undefined when the power is turned on, so it is necessary to read the switch information from the outside. An external config ROM (Configuration ROM) is required. In PolarFire SoC, the Flash cell itself remembers the switch information, so no external config ROM is required.

Low power consumption and high radiation resistance

The points of differentiation from competing FPGAs are (A) low power consumption, (B) space saving, and (C) high radiation resistance. As an example of (A), the power consumption of the router (ROUTER) is using 220kLE, transceiver: 10 Gbps x 16 lane, 160MHz operation and the remote radio unit (RRU) is using 140kLE, transceiver: 9.8 Gbps x 16 lane, 275MHz). Figure 6 shows a comparison of the power consumption of (operation) with competitors.

“The static power consumption is significantly lower than that of competing FPGAs, and the power consumption of the transceiver is also about half lower. As a result, it is possible to reduce the power consumption by about 40% to 50%.” [6]. Microchip FPGAs are said to be ideal for battery-powered apps with a sealed enclosure that is difficult to release heat.

Figure 6 Comparison of Microsemi Polar Fire Power Consumption and Competing Midrange FPGA Power Consumption in Two Application Cases [6]

Figure 6 Comparison of Microsemi Polar Fire Power Consumption and Competing Midrange FPGA Power Consumption in Two Application Cases [6]

When radiation interacts with a semiconductor, electron-hole pairs are generated along the passage path (Figure 7) [8]. When this reaches the charge holding node of SRAM (Figure 3, left figure), SRAM information can be inverted. The amount of radiation increases as it goes up in the sky, and even more in outer space.

The transient malfunction of a semiconductor device caused by radiation is called SEE (Single Event Effect). SEE is a general term for SEU (Single Event Upset) and SEL (Single Event Latch-ups).

The wiring program method of Microsemi FPGA uses the Flash method (center of Figure 3) instead of the SRAM method. Since the amount of electric charge stored in the Flash cell is large, it seems that SEE is much less likely to occur. In other words, Microsemi FPGA has high radiation resistance.

RT PolarFire is a product that incorporates the radiation-resistant technology of the highly radiation-resistant FPGA “RTG4” announced in 2015 into the low-power consumption mid-range FPGA “PolarFire” announced in 2017 [7].

RTG4 is widely used in aerospace applications because it is less likely to cause SEU (Single Event Upset), SEL (Single Event Latch-ups), and configuration data corruption due to radiation. They are currently developing a smart embedded vision concept with the aim of highly reliable image application.

Figure 7 Three radiations that cause SEE on the ground [8]

I think that Microsemi FPGAs have a solid track record in the aerospace military market, but the market size is limited. Taking advantage of the high reliability we have cultivated was probably a strategy to expand the customers to vision solutions for in-vehicle medical care and robots.


“Latest Trends in Atomic Switch FPGA Technology”

Next, let’s take a closer look at the talk about the new non-volatile FPGA device. Mr. Toshiji Sakamoto from Nanobridge Semiconductor (NBS) gave a lecture titled “Latest Trends in Atomic Switch FPGA Technology”. NBS is a venture company established by NEC researchers in September 2019 [9].

Operating principle

NanoBridge is a technology that controls the precipitation and dissolution of metal atoms in a solid electrolyte by an applied voltage, and creates and eliminates nanometer-sized metal bridges between LSI wiring to create a switch on / off state.

FPGA that can reconfigure the circuit after manufacturing, has low power consumption, high radiation resistance and temperature resistance because the repetitive circuit can be rewritten and no power is required to maintain the on / off state (nonvolatile). It is increasingly attracting attention as the most suitable technology for Field Programmable Gate Array and memory [10].

FPGAs that use NanoBridge as the FPGA wiring program element are called NB-FPGA (NanoBrideg FPGA) or AS-FPGA (Atomic Switch FPGA). In Figure 8 the operating principle is shown on the left. When a positive voltage is applied to the copper electrode side, the copper of the electrode is ionized and moves in the polymer solid electrolyte to form a bridge between the two electrodes. As a result, NanoBridge transitions from a high resistance (off) state to a low resistance (on) state.

On the other hand, when a negative voltage is applied to the copper electrode side, the copper atoms forming the crosslinks are recovered on the copper electrode side and transition to a high resistance state. NanoBridge can be rewritten repeatedly and does not require power to maintain the on / off state (nonvolatile). The life of the number of rewrites is about 1,000, which is considered to be sufficient for FPGA wiring program applications. It also has high radiation resistance.

Figure 8 Left: Operating principle of NanoBridge technology, Right: NB-FPGA chip photo [10]

Figure 8 Left: Operating principle of NanoBridge technology, Right: NB-FPGA chip photo [10]

Figure 9 Left: Operational principle of atomic switch, Right: Cross-sectional electron micrograph of NB-FPGA including atomic switch (CAS red frame) [9]

28nm generation NB-FPGA SoC under development

The need for AI processing in Edge / IoT terminals is increasing, and a 28nm generation SoC chip that performs CNN inference processing in Edge / IoT terminals is under development in the NEDO project. CNN inference accelerators using FGPA can obtain higher power efficiency than CPU and GPU.

CNN accelerators using FPGAs require FPGAs of 100k LUT (Look-Up Table: programmable logic gate) or higher. The SoC chips under development are (1) CNN-Accelerator (using NB-FPGA block with 171k LUT), (2) RISC-V CPU, (3) Code ROM (using NB memory), (4) SRAM, (5) IO / SPI / USB / Ethernet, etc. are integrated.

Power is reduced by intermittent operation using non-volatility. Compared to the 40nm generation NB-FPGA, the chip area is reduced by about 75%, demonstrating 5 times higher logic density and higher power efficiency. In addition, the mapping tool from RTL to FPGA supports logic synthesis, automatic placement and routing, and others.

In my opinion, methods other than deep learning, which have a smaller amount of data and shorter processing time than deep learning, especially sparse modeling, are attracting attention as one solution [11] [12]. It may be suitable for space applications where the logic scale is limited.

Regarding NB-FPGA chip manufacturing, 65nm generation products are integrated production at domestic fabs (semiconductor manufacturing companies). For the 40nm and 28nm generation products, the base (lower layer than the transistor layer and NB switch element layer) is manufactured at the overseas fab, and the upper ground (upper layer than the NB switch layer) is manufactured at the domestic fab.

Case study

NB-FPGA 40nm generation products were used for robots (Inaba Laboratory, University of Tokyo) and artificial satellites (JAXA demonstration satellite RAPIS-1) [13]. In the case of JAXA Small Demonstration Satellite No. 1 (RAPIS-1), three evaluation circuits were mounted on the “Deployment Confirmation Monitor Camera” (CMRD2) module.

They reported that in (1) soft error evaluation circuit, (2) image compression processing of data captured by HD CMOS sensor, and (3) partial rewriting of NV-FPGA, not a single error has occurred in any item for about one year.

Currently, FPGAs are not supplied domestically within Japan. Mr. Sakamoto hopes to realize domestic production and contribute to the Japanese space industry. Using this demonstration as a foothold, he would like to advance into fields that require high reliability, such as automobiles and medical care, and also want to focus on expanding into consumer products [14].

As mentioned by the speaker, the author felt two major issues: (1) enhancement of NB-FPGA design tools, and (2) establishment of cost-competitive manufacturing.

Regarding (1), an NB-FPGA design tool comparable to the Xilinx Vivado and Intel Quartus design tools will be required for general users to use. Regarding (2), he is investigating how to make cost-competitive manufacturing in Japan without a semiconductor manufacturing factory that can manufacture 28nm generation substrates. Although it is a difficult task, I would like to see the NB-FPGA, which has excellent characteristics, be widely commercialized.


Figure 10 Image taken by “Monitor camera for deployment confirmation” (CMRD2) of JAXA “Small demonstration satellite No. 1” (RAPIS-1) [13]


[1] AIST Consortium
Author’s Note: No.35 is Non-Volatile Field-Programmable Gate Array (NV-FPGA) Initiative

[2] Introduction to FPGA Design for Embedded Systems 7. Microsemi Single-chip FPGA solutions

[3] Microchip FPGA and SoC product families

[4] Microchip PolarFire FPGA

[5] Microchip announces RISC-V instruction set architecture-based SoC FPGA development kit

[6] Macnica Microchip’s non-volatile FPGA “Polar Fire”

[7] AI processing in space, US microchip increases the computing power of radiation-resistant FPGA by 5 times

[8] Kazuyoshi Kobayashi, Semiconductor Resistance Test-Actual Evaluation of Single Event Resistance by Accelerator-

[9] Nanobridge Semiconductor Co., Ltd. Abbreviation: NBS

[10] NEC and AIST develop LSI equipped with “NanoBridge (R)” technology with excellent radiation resistance for use in space environment

[11] AI learning at the edge is possible Scratch detection with Japanese traditional Japanese paper “Crane”

[12] Training AI models on the edge

[13] Small demonstration satellite No. 1 RAPIS-1 is in initial operation!

[14] Innovative FPGA aiming to be applied to the automobile and medical fields, etc., where we want to prove high reliability using space.